Parity Generators and Checkers
Devices in the parity generator and checker logic family are component-level devices used to evaluate the number of bits in a digital word that are set to 1, and generate (or evaluate) an additional parity bit which indicates whether the number of bits in the word set to 1 is even or odd. This function is commonly used as a simple means of detecting data errors that may have been introduced during transmission.
ON Semiconductor DM74AS280MX
IC 9-BIT GEN/CHKER 14SOIC
0
ON Semiconductor 74F280SCX
IC 9-BIT GEN/CHKER 14SOIC
0
ON Semiconductor DM74AS286MX
IC 9-BIT GEN/CHKER 14SOIC
0
ON Semiconductor DM74AS280M
IC 9-BIT GEN/CHKER 14SOIC
0
ON Semiconductor 74F280SJX
IC 9-BIT GEN/CHKER 14SOP
0
ON Semiconductor 74F280SJ
IC 9-BIT GEN/CHKER 14SOP
0
ON Semiconductor 74F280SC
IC 9-BIT GEN/CHKER 14SOIC
0
ON Semiconductor 74AC280SJX
IC 9-BIT GEN/CHKER 14SOP
0